All,
I'm trying to modify a Makefile to use a embedded cross compiler instead of the PC's compiler. The Makfile does not have the normal CC or CXX variables. In fact, it appears that is calls another makefile with the variable '#${MAKE}'. How can I override the '#${MAKE}' variable to force the makefile to use a diffent compliler?
Thanks In Advance,
# GNU Make solution makefile autogenerated by Premake
# Type "make help" for usage help
ifndef config
config=debug
endif
export config
PROJECTS := json openjaus
.PHONY: all clean help $(PROJECTS)
all: $(PROJECTS)
json:
#echo "==== Building json ($(config)) ===="
#${MAKE} --no-print-directory -C .build -f json.make
openjaus: json
#echo "==== Building openjaus ($(config)) ===="
#${MAKE} --no-print-directory -C .build -f openjaus.make
I edited the Makefile based on Rob's comments, now I'm receiving the message below, not sure what to do?
make[1]: Nothing to be done for `/home/botbear/openwrt/trunk/staging_dir/toolchain-arm_v6k_gcc-linaro_uClibc-0.9.32_eabi/bin/arm-openwrt-linux-uclibcgnueabi-g++'.
You'd have to look inside json.make and openjaus.make to see how they build programs. If they use the conventional variables, you might be able to do something like:
${MAKE} CC=/usr/bin/gcc-arm CXX=/usr/bin/g++-arm --no-parent-directory ...
Related
I'm using CMake with the GNU Make generator on a project of mine, and then want to build it - verbosely.
I'm interested in lines which actually produce things, and not interested in lines such as:
gmake[2]: Entering directory '/some/where'
gmake[2]: Leaving directory '/some/other/place'
nor the lines saying:
cd /some/where && /path/to/cmake/bin/cmake -E cmake_link_script CMakeFiles/some.dir/link.txt --verbose=1
as those are "wrapping" the actual work that will happen when cmake runs that script (e.g. calls a linker executable such as gcc).
I don't mind very much the percentage headers such as:
[ 97%] Building CXX object /path/to/proj/CMakeFiles/something.dir/foo.o
i.e. if your solution removes them, then fine, if it keeps them - also fine.
I've read answers and comments on this question: Using CMake with GNU Make: How can I see the exact commands?, and the best I've come up with so far is:
MAKEFLAGS="$MAKEFLAGS --no-print-dir" cmake --build build_dir/ --verbose
The --verbose gives you maximum (?) verbosity, with everything you don't want. Then, the --no-print-dir is picked up by GNU Make, making it avoid the Entering/Leaving Directory messages.
Can I do better, and actually avoid the cd and the cmake -E commands?
Notes:
I realize I can use maximum verbosity, then filter using grep. That's not what I want - I want the lines not to be emitted in the first place.
Nothing may be hard-coded into the CMakeLists.txt file; everything must be done via the command-line, after CMake configuration.
You can discover for yourself that there is no way to do what you want.
Since cmake is just generating makefiles, and it's make that is actually running the recipes and printing the output, you need to look at the makefile and see how the rules are constructed. If you find a sample rule for a link line for example you will see it looks like this:
myexecutable: ...
#$(CMAKE_COMMAND) -E cmake_echo_color --switch=$(COLOR) --green --bold --progress-dir=/mydir/CMakeFiles --progress-num=$(CMAKE_PROGRESS_2) "Linking CXX executable myexecutable"
cd /mydir && $(CMAKE_COMMAND) -E cmake_link_script CMakeFiles/myexecutable.dir/link.txt --verbose=$(VERBOSE)
Note that there is no special variable, or token, or anything appearing in this recipe before the cd /mydir ... text.
So, there is absolutely no way to control how this particular recipe is printed, separately from how all the other recipes are printed. You either get them all, or you get none of them.
On attempting to build wxWidgets 3.1.0 libraries, I am getting this error
ar: gcc_mswu\moolib_fontmap.o: No such file or directory
A file does exists with a slightly different spelling
Directory of C:\Users\James\code\wxwidgets-3.1.0\build\msw\gcc_mswu
2017-01-05 02:01 PM 98,886 monolib_fontmap.o
It looks like a typo in the makefile, or like a letter is missed reading the makefile. Is that possible?
Except: if I redirect the console output to a file and open in an editor , the correct spelling shows up:
So the correct command is going to the linker, but the linker is looking for a garbled filename!
Here is the complete recipe for what I am doing:
Download wxWidgets source code from https://github.com/wxWidgets/wxWidgets/releases/download/v3.1.0/wxWidgets-3.1.0.7z
Unpack to a folder. On my system, I use C:\Users\James\code\wxwidgets-3.1.0
Open a command window.
cd to the code::blocks mingw folder. On my system this is C:\Program Files (x86)\CodeBlocks16\MinGW
Type mingwvars.bat
cd to wxwidgets folder. On my system C:\Users\James\code\wxwidgets-3.1.0
cd to ./build/msw
Type mingw32-make SHELL=CMD.exe -j4 -f makefile.gcc BUILD=release UNICODE=1 SHARED=0 MONOLITHIC=1
This seems to be the same problem as the one mentioned in the wiki. Apparently there is a bug in mingw32-make with very long command lines which makes it (sometimes?) eat characters in them...
Yes. Applying the recipe in the link you posted fixed the problem. Here are the details:
modify makefile.gcc as following:
From:
ifeq ($(MONOLITHIC),1)
ifeq ($(SHARED),0)
$(LIBDIRNAME)\libwx$(PORTNAME)$(WXUNIVNAME)$(WX_RELEASE_NODOT)$(WXUNICODEFLAG)$(WXDEBUGFLAG)$(WX_LIB_FLAVOUR).a: $(MONOLIB_OBJECTS)
if exist $# del $#
ar rcu $# $(MONOLIB_OBJECTS)
ranlib $#
endif
endif
Replace second occurence of $(MONOLIB_OBJECTS) with gcc_mswu\monolib*.o:
ifeq ($(MONOLITHIC),1)
ifeq ($(SHARED),0)
$(LIBDIRNAME)\libwx$(PORTNAME)$(WXUNIVNAME)$(WX_RELEASE_NODOT)$(WXUNICODEFLAG)$(WXDEBUGFLAG)$(WX_LIB_FLAVOUR).a: $(MONOLIB_OBJECTS)
if exist $# del $#
ar rcu $# gcc_mswu\\monolib*.o
ranlib $#
endif
endif
I'm trying to set up a toolchain for CMake and have made some progress (it's getting the right compiler and all), but I've run into a problem with the -I (include directories directive).
The compiler I'm using doesn't understand -I, it understands -i. What I don't understand is where to change this so that CMake builds the makefile with the -i rather than the -I.
Any help would be greatly apprecaited
Somewhere in your CMakeLists.txt file, you should add the following line:
set(CMAKE_INCLUDE_FLAG_C "-i")
This will change your include flag from the default of -I to -i. Do CMAKE_INCLUDE_FLAG_CXX for C++.
I say this with the caveat that you might want to wrap this in a if that only does this for the Cosmic compiler.
CMake sets this to -I by default in the file CMakeGenericSystem.cmake... search your cmake install dir this file and you will see the CMake defaults for several settings inside. If a compiler has to modify this, it will be in the Compiler folder in the same dir as CMakeGenericSystem.cmake. I'm willing to bet that there is nothing implemented in the Compiler folder for the Cosmic compiler.
is there a way to set a output-directory for making kernel-modules inside my makefile?
I want to keep my source-direcory clean from the build-files.
KBUILD_OUTPUT and O= did not work for me and were failing to find the kernel headers when building externally.
My solution is to symlink the source files into the bin directory, and dynamically generate a new MakeFile in the bin directory. This allows all build files to be cleaned up easily since the dynamic Makefile can always just be recreated.
INCLUDE=include
SOURCE=src
TARGET=mymodule
OUTPUT=bin
EXPORT=package
SOURCES=$(wildcard $(SOURCE)/*.c)
# Depends on bin/include bin/*.c and bin/Makefile
all: $(OUTPUT)/$(INCLUDE) $(subst $(SOURCE),$(OUTPUT),$(SOURCES)) $(OUTPUT)/Makefile
make -C /lib/modules/$(shell uname -r)/build M=$(PWD)/$(OUTPUT) modules
# Create a symlink from src to bin
$(OUTPUT)/%: $(SOURCE)/%
ln -s ../$< $#
# Generate a Makefile with the needed obj-m and mymodule-objs set
$(OUTPUT)/Makefile:
echo "obj-m += $(TARGET).o\n$(TARGET)-objs := $(subst $(TARGET).o,, $(subst .c,.o,$(subst $(SOURCE)/,,$(SOURCES))))" > $#
clean:
rm -rf $(OUTPUT)
mkdir $(OUTPUT)
If you are building inside the kernel tree you can use the O variable:
make O=/path/to/mydir
If you are compiling outside the kernel tree (module, or any other kind of program) you need to change your Makefile to output in a different directory. Here a little example of a Makefile rule which output in the MY_DIR directory:
$(MY_DIR)/test: test.c
gcc -o $# $<
and then write:
$ make MY_DIR=/path/to/build/directory
The same here, but I used a workaround that worked for me:
Create a sub-directory with/for every arch name (e.g. "debug_64").
Under "debug_64": create symbolic link of all .c and .h files. Keeping the same structure.
Copy the makefile to "debug_64" and set the right flags for 64 Debug build, e.g.
ccflags-y := -DCRONO_DEBUG_ENABLED
ccflags-y += -I$(src)/../../../lib/include
KBUILD_AFLAGS += -march=x86_64
Remember to set the relative directories paths to one level down, e.g. ../inc will be ../../inc.
Repeat the same for every arch/profile.
Now we have one source code, different folders, and different make files.
By the way, creating profiles inside make files for kernel module build is not an easy job, so, I preferred to create a copy of makefile for every arch.
Basically, I have a file 'blah.txt'. That files gets parsed by a 'compiler' and from it will generate N output .c files. I want a makefile that will from that .txt file generate the c files then compile all of them and archive them in a libmystuff.a
I tought of something like this :
all: dogen libmystuff.a
dogen: source.txt
mycompiler $^
libmystuff.a: $(addsuffix .o, $(shell ls *.c))
$(AR) rcs $# $^
.PHONY: dogen
But obviously that doesn't work because the dependencies are evaluated at the start and at that point the *.c just doesn't yield anything yet since they don't exist.
Does anyone see how to accomplish that (without listing all the generated *.c explicitely) ?
Use sentry "makefile" to force make to re-read makefile and substitute correct list at *.c:
include sources-sentry
sources-sentry: source.txt
mycompiler $^
touch $#
libmystuff.a: $(addsuffix .o, $(shell ls *.c))
$(AR) rcs $# $^
include directive is used to include other makefiles (just like C's #include). It has a nice pecularity that if makefile it includes is a target itself, make program first considers it as a target and tries to update. If it is not up-to-date, make invokes the commands needed to update it and then re-reads makefile, substituting all the variables again.
Thus, if source.txt changed since the last time you processed it (the time being recorded as timestamp of sources-sentry file), the sources will be updated and make will be re-invoked, the *.c being substituted to the updates set of c-files.
Pavel Shved is right(*), you must rerun Make. Here is a trick I'm rather proud of. It will handle dependencies on objects that may not yet exist, and won't run unnecessarily.
SOURCES = $(wildcard *.c)
OBJECTS = $(SOURCES:.c=.o)
all: libmystuff.a
ifeq ($(MAKELEVEL),0)
libmystuff.a: source.txt
mycompiler $^
#$(MAKE) -s $#
else
libmystuff.a: $(OBJECTS)
$(AR) rcs $# $^
endif
(*) My old nemesis, we meet again.
EDIT:
If some other make calls this make... I hadn't thought of that. But I think this will solve it:
SOURCES = $(wildcard *.c)
OBJECTS = $(SOURCES:.c=.o)
all: libmystuff.a
libmystuff.a: source.txt
mycompiler $^
#$(MAKE) -s phonyLib
.PHONY: phonyLib
phonyLib: $(OBJECTS)
$(AR) rcs libmystuff.a $^
(Yes, I know, if you feel an urge to build a file called "phonyLib" you won't be able to do it with this makefile, but let's not be perverse.)
If your .c files are only produced by the .txt, then you can let the libmystuff.a depend on the txt, and evaluate the $(shell ls *.c) in the rule body instead.