errors while using two process in one entity vhdl - process

Question

I am trying to write a signal generator with VHDL and state machine approach. it needs to have two processes in an entity and I am doing everything just as same as the course I've passed but I am getting some errors around my process and I think something must be wrong with it. this is the code
entity pulse_generator is
port(clk : in std_logic;
output: out std_logic);
end pulse_generator;
architecture Behavioral of pulse_generator is
type state is (one, two, three, four);
signal nxt, pre: state;
begin
--upper
p1: process(clk)
begin
if (falling_edge(clk))then
pre <= nxt;
end if
end process p1;
--lower
p2: process(pre)
variable count: integer range 0 to 500;
begin
case pre is
when one =>
output <= '0';
count := count+1;
if (count = 300)then
nxt <= two;
count := 0;
else nxt <= one;
end if;
when two =>
output <= '1';
count := count+1;
if (count = 400)then
nxt <= three;
count := 0;
else nxt <= two;
end if;
when three =>
output <= '0';
count := count+1;
if (count = 500)then
nxt <= four;
count := 0;
else nxt <= three;
end if;
when four =>
output <= '1';
count := count+1;
if (count = 200)then
nxt <= one;
count := 0;
else nxt <= four;
end if;
end case;
end process p2;
end Behavioral;
and these are the errors
ERROR:HDLCompiler:806 - Line 19: Syntax error near "end".
ERROR:HDLCompiler:806 - Line 22: Syntax error near "process".
ERROR:HDLCompiler:806 - Line 23: Syntax error near "variable".
ERROR:HDLCompiler:806 - Line 59: Syntax error near "process".
ERROR:HDLCompiler:806 - Line 61: Syntax error near "Behavioral"
what am I doing wrong?