I keep getting errors below in ISE, and can not figure out the real problems. anyone has any clues?
error messages:
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 29: Syntax error near "posedge".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 39: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 43: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 47: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 50: Syntax error near "end".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 54: Syntax error near "posedge".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 64: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 68: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 72: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 75: Syntax error near "end".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 88: Syntax error near "posedge".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 98: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 102: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 106: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 109: Syntax error near "end".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 113: Syntax error near "posedge".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 123: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 127: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 131: Syntax error near "<=".
and here is my code:
`timescale 1ns/1ps
module QFC_A #
(
parameter SPI_CYCLE = 100000,
parameter MASTER_ID = 8'h66,
parameter SLAVE_ID = 8'h66
)
(
input i_axi_lite_s_aclk,
input i_rst,
input i_din,
output o_en,
output o_dout
);
reg [255:0] r_frame_message;
reg [3:0] r_cnt_message;
wire [31:0] w_frame_word_message;
wire w_message_rd_en;
wire w_id_match_message;
wire w_message_empty;
wire w_message_ready;
always # (posedge i_axi_lite_s_aclk & posedge i_rst)
begin
if (i_rst)
begin
r_frame_message <= 256'h0;
end
else
begin
if (w_id_match_message & (r_cnt_message != 4'hf))
begin
r_frame_message <= {224'h0, w_frame_word_message};
end
else if (w_message_rd_en & w_message_empty)
begin
r_frame_message <= 256'h0;
end
else if (w_message_rd_en)
begin
r_frame_message <= {r_frame_message[223:0], w_frame_word_message};
end
end
end
assign w_id_match_message = (w_frame_word_message[23:16] == MASTER_ID)? 1'b1 : 1'b0;
always # (posedge i_axi_lite_s_aclk & posedge i_rst)
begin
if (i_rst)
begin
r_cnt_message <= 4'h0;
end
else if (w_message_rd_en)
begin
if (w_id_match_message)
begin
r_cnt_message <= 4'h0;
end
else if (r_cnt_message == 4'hf)
begin
r_cnt_message <= 4'h0;
end
else
begin
r_cnt_message <= r_cnt_message + 4'h1;
end
end
end
assign w_message_ready = (r_cnt_message == 4'hf & ~w_send_ready)? 1'b1 : 1'b0;
reg [255:0] r_frame_data;
reg [3:0] r_cnt_data;
wire [31:0] w_frame_word_data;
wire w_data_rd_en;
wire w_id_match_data;
wire w_data_empty;
wire w_data_ready;
always # (posedge i_axi_lite_s_aclk & posedge i_rst)
begin
if (i_rst)
begin
r_frame_data <= 256'h0;
end
else
begin
if (w_id_match_data & (r_cnt_data != 4'hf))
begin
r_frame_data <= {224'h0, w_frame_word_data};
end
else if (w_data_rd_en & w_data_empty)
begin
r_frame_data <= 256'h0;
end
else if (w_data_rd_en)
begin
r_frame_data <= {r_frame_data[223:0], w_frame_word_data};
end
end
end
assign w_id_match_data = (w_frame_word_data[23:16] == MASTER_ID)? 1'b1 : 1'b0;
always # (posedge i_axi_lite_s_aclk & posedge i_rst)
begin
if (i_rst)
begin
r_cnt_data <= 4'h0;
end
else if (w_data_rd_en)
begin
if (w_id_match_data)
begin
r_cnt_data <= 4'h0;
end
else if (r_cnt_data == 4'hf)
begin
r_cnt_data <= 4'h0;
end
else
begin
r_cnt_data <= r_cnt_data + 4'h1;
end
end
end
assign w_data_ready = (r_cnt_data == 4'hf & ~w_send_ready)? 1'b1 : 1'b0;
reg [255:0] r_frame_rec;
reg [3:0] r_cnt_rec;
wire[31:0] w_frame_word_rec;
wire w_rec_en;
wire w_id_match_rec;
wire w_rec_ready;
wire w_rec_success;
always # (posedge i_axi_lite_s_aclk & posedge i_rst)
begin
if (i_rst)
begin
r_frame_rec <= 256'h0;
end
else
begin
if (w_id_match_rec & (r_cnt_rec != 4'hf))
begin
r_frame_rec <= {224'h0, w_frame_word_rec};
end
else if (w_rec_en)
begin
r_frame_rec <= {r_frame_rec[223:0], w_frame_word_rec};
end
end
end
assign w_id_match_rec = (w_frame_word_rec[23:16] == SLAVE_ID)? 1'b1 : 1'b0;
always # (posedge i_axi_lite_s_aclk & posedge i_rst)
begin
if (i_rst)
begin
r_cnt_rec <= 4'h0;
end
else if (w_rec_en)
begin
if (w_id_match_rec)
begin
r_cnt_rec <= 4'h0;
end
else if (r_cnt_rec == 4'hf)
begin
r_cnt_rec <= 4'h0;
end
else
begin
r_cnt_rec <= r_cnt_rec + 4'h1;
end
end
end
assign w_rec_ready = (r_cnt_rec == 4'hf)? 1'b1 : 1'b0;
assign w_rec_success = ((w_rec_ready) & (r_frame_rec[251] == 1'b1) & (checksum(r_frame_rec[239:16]) == r_frame_rec[15:0]))? 1'b1 : 1'b0;
reg [2:0] r_current_state;
reg [2:0] r_next_state;
reg [16:0] r_cycle_timer;
reg [14:0] r_trans_timer;
reg [1:0] r_cycle_s;
reg [223:0] r_payload;
reg [255:0] r_frame_send;
wire w_cycle;
wire w_cycle_pos;
wire w_state_start;
localparam IDLE = 3'h0;
localparam SEND_MSG = 3'h1;
localparam RESEND_MSG = 3'h2;
localparam SEND_DATA = 3'h3;
localparam RCG_ACK = 3'h4;
localparam CHANGE_TLG = 3'h5;
localparam ABORT_MSG = 3'h6;
always # (posedge i_axi_lite_s_aclk & posedge i_rst)
begin
if (i_rst)
begin
r_cycle_timer <= 16'h0;
end
else if (r_cycle_timer < SPI_CYCLE)
begin
r_cycle_timer <= r_cycle_timer + 16'h1;
end
else
begin
r_cycle_timer <= 16'h0;
end
end
assign w_cycle = (r_cycle_timer == SPI_CYCLE)? 1'b1 : 1'b0;
always # (posedge i_axi_lite_s_aclk & posedge i_rst)
begin
if(i_rst)
begin
r_cycle_s <= 2'h0;
end
else
begin
r_cycle_s <= {r_cycle_s[0], w_cycle};
end
end
assign w_cycle_pos = (~r_cycle_s[1] & r_cycle_s[0]);
function reg [15:0] checksum (input reg [223:0] r_frame)
begin
integer i;
reg [15:0] r_sum_1;
reg [15:0] r_sum_2;
r_sum_1 = 16'hff;
r_sum_2 = 16'hff;
for (i = 0; i < 28; i++)
begin
r_sum_1 = r_sum_1 + r_frame[(223-8*i)-:8];
r_sum_2 = r_sum_1 + r_sum_2;
if (i == 20)
begin
r_sum_1 = ( r_sum_1 >> 8 ) + ( r_sum_1 & 8'hff);
r_sum_2 = ( r_sum_2 >> 8 ) + ( r_sum_2 & 8'hff);
end
end
r_sum_1 = ( r_sum_1 >> 8 ) + ( r_sum_1 & 8'hff);
r_sum_2 = ( r_sum_2 >> 8 ) + ( r_sum_2 & 8'hff);
r_sum_1 = ( r_sum_1 >> 8 ) + ( r_sum_1 & 8'hff);
r_sum_2 = ( r_sum_2 >> 8 ) + ( r_sum_2 & 8'hff);
checksum = (r_sum_1 << 8) | r_sum_2;
end
endfunction
always # (*)
begin
case (r_current_state)
IDLE: begin
r_next_state = SEND_DATA;
r_frame_send = {8'h90, MASTER_ID, 240'h0};
end
SEND_MSG: begin
r_next_state = RCG_ACK;
if (w_state_start)
begin
w_message_rd_en = 1'b1;
w_send_ready = 1'b0;
w_state_start = 1'b0;
end
if (r_frame_message == 256'h0)
begin
w_message_rd_en = 1'b0;
r_frame_send = {r_frame_send[], MASTER_ID, 240'h0};
end
else if
end
RCG_ACK: begin
if (w_rec_success)
begin
r_next_state = CHANGE_TLG;
end
else if (r_resend_cnt == 2'b11)
begin
r_next_state = ABORT_MSG;
end
end
endcase
end
endmodule
The likely cause of this error is from the & in # (posedge i_axi_lite_s_aclk & posedge i_rst). It is illegal syntax and I am guessing it is confusing the parser, making the error appear by the non-blocking assignment (<=). Change these & to or (I believe IEEE 1364-2001 also supports , as a sensitivity list separator but I do not have my LRM on hand to validate).
Eg: # (posedge i_axi_lite_s_aclk or posedge i_rst)
There are plenty of other syntax errors. Missing semicolon in the function header, dangling else if, undeclared identifiers, etc. I'm not going to fix them for you.
FYI:
& is a bitwise and operator, which is different then the logical and operator &&. You are using & in places where && would be recommended. I suggest you study the differences between logical and bitwise operators.
For many synthesizers using ? : creates an explicit 2-to-1 mux. In all the cases you use ? : the select value is the same as the output value. So you may just be wasting space.
I would suggest changing assign w_message_ready = (r_cnt_message == 4'hf & ~w_send_ready)? 1'b1 : 1'b0; to assign w_message_ready = (r_cnt_message == 4'hf && !w_send_ready);. Functionally they are identical, but the latter is more explicit and concise.
Related
I am trying to write a signal generator with VHDL and state machine approach. it needs to have two processes in an entity and I am doing everything just as same as the course I've passed but I am getting some errors around my process and I think something must be wrong with it. this is the code
entity pulse_generator is
port(clk : in std_logic;
output: out std_logic);
end pulse_generator;
architecture Behavioral of pulse_generator is
type state is (one, two, three, four);
signal nxt, pre: state;
begin
--upper
p1: process(clk)
begin
if (falling_edge(clk))then
pre <= nxt;
end if
end process p1;
--lower
p2: process(pre)
variable count: integer range 0 to 500;
begin
case pre is
when one =>
output <= '0';
count := count+1;
if (count = 300)then
nxt <= two;
count := 0;
else nxt <= one;
end if;
when two =>
output <= '1';
count := count+1;
if (count = 400)then
nxt <= three;
count := 0;
else nxt <= two;
end if;
when three =>
output <= '0';
count := count+1;
if (count = 500)then
nxt <= four;
count := 0;
else nxt <= three;
end if;
when four =>
output <= '1';
count := count+1;
if (count = 200)then
nxt <= one;
count := 0;
else nxt <= four;
end if;
end case;
end process p2;
end Behavioral;
and these are the errors
ERROR:HDLCompiler:806 - Line 19: Syntax error near "end".
ERROR:HDLCompiler:806 - Line 22: Syntax error near "process".
ERROR:HDLCompiler:806 - Line 23: Syntax error near "variable".
ERROR:HDLCompiler:806 - Line 59: Syntax error near "process".
ERROR:HDLCompiler:806 - Line 61: Syntax error near "Behavioral"
what am I doing wrong?
[Yosys 0.8]
A colleague of mine threw some random verilog code to Yosys to see how it reacts.
Here it is:
module top(input clk, input led, output led2, output to_port1,output [24:0] to_port2);
reg ctr = 0;
reg[24:0] counter = 2;
always#(posedge clk) begin
if (ctr == 1) begin
ctr <= 0;
counter <= counter + 1;
end
else
ctr <= 1;
end
assign led2 = ctr;
assign to_port1 = led;
assign to_port2 = counter;
endmodule
and Yosys, with command yosys -o synth.v x.v throws:
module top(clk, led, led2, to_port1, to_port2);
reg [24:0] _0_;
reg _1_;
reg [24:0] _2_;
reg _3_;
wire [31:0] _4_;
wire _5_;
input clk;
reg [24:0] counter;
reg ctr;
input led;
output led2;
output to_port1;
output [24:0] to_port2;
assign _4_ = counter + 32'd1;
assign _5_ = ctr == 32'd1;
always #* begin
_3_ = 1'h0;
end
always #* begin
end
always #({ }) begin
ctr <= _3_;
end
always #* begin
_2_ = 25'h0000002;
end
always #* begin
end
always #({ }) begin
counter <= _2_;
end
always #* begin
_1_ = ctr;
_0_ = counter;
casez (_5_)
1'h1:
begin
_1_ = 1'h0;
_0_ = _4_[24:0];
end
default:
_1_ = 1'h1;
endcase
end
always #(posedge clk) begin
ctr <= _1_;
counter <= _0_;
end
assign led2 = ctr;
assign to_port1 = led;
assign to_port2 = counter;
endmodule
Some constructs end up being complicated. This result code above cannot be compiled by recent verilog compilers when the original can.
Why the always #({ }) begin construct and empty always #* begin?
Is there an option we missed?
Thanks
In general you should always run proc (-p proc) between reading and writing Verilog, due to the nature of Yosys' internal representation of the read-in Verilog
I have an HDL Block in which the output follows the input in such a way that when input signal is binary 0, output remains 0 but when input turns 1, output turns 1 for a preset number of clock cycles (signal_length). i.e. input may remain high for suppose 65 or 66 clock cycles but output should remain high for preset number of clock cycles. I tried to accomplish the task with Verilog. But I am having an error and I don’t know how to rectify. Hope someone can help.
module last_ind
#(
parameter MAX_LENGTH = 262144,
parameter signal_length
)
(
input clk,
input [17:0] pkt_length,
input tdata,
output tlast
);
reg [17:0] cnt = 0;
always # (posedge clk)
begin
if ((tdata==1) && (cnt<signal_length))
tlast <= 1;
else
cnt <= 0;
end
assign cnt <= cnt + 1'b1;
endmodule
maybe something like this will do. It should keep the signal up for the signal_length cycles and will reset when tdata gets '0'. You decide on the correct protocol though.
reg [17:0] cnt = signal_length;
always # (posedge clk) begin
if (cnt < signal_lenth)
cnt <= cnt + 1;
else if (cnt == signal_length + 1 && tdata == 1 && tlast == 0) begin
cnt <= 0;
tlast <= 1;
end
else if (tdata == 0) begin
cnt <= sighal_length + 1;
tlast <= 0;
end
else
tlast <= 0;
end
I want to give only one strobe pulse of 2 clock cycles wide everytime a data is placed on the output. I am not able to implement the logic in verilog.Here is the pseudocode i have written
reg [1:0] step = 2'b00;
always # (posedge clock)
begin
case (switch)
1'b0 : begin
load data 1;
flag <= 1;
end
1'b0 : begin
load data 2;
flag <= 1;
end
endcase
if (flag == 1)
case (step)
2'b00 : strobe high;
2'b01 : wait;
2'b10 : strobe low;
2'b11 : flag <=0;
endcase
end
If I do this the reg step is becoming 2'b11 after properly giving the strobe pulse after the first data, but I am not able to reset it to zero again for the second data, so when second time flag is set high the step variable only enters the last case. If I set step <= 2'b00 elsewhere the strobe output is constantly changing with each clock cycle. I want only one pulse.
Actual Code :
`timescale 1ns / 1ps
module test3(
input i_clock,
input i_switch,
output reg [7:0] o_data = 8'b00001111,
output reg o_strobe = 1'b0
);
reg flag = 1'b0;
reg [1:0] step = 2'b00;
always # (posedge i_clock)
begin
if (flag == 1'b0)
begin
case (i_switch)
1'b0 : begin
o_data [7:0] <= 32'b00000000;
flag <= 1'b1;
end
1'b1 : begin
o_data [7:0] <= 32'b11111111;
flag <= 1'b1;
end
endcase
end
else if (flag == 1)
begin
case (step)
2'b00 : begin
o_strobe <= 1'b1;
step <= 2'b01;
end
2'b00 : begin
step <= 2'b10;
end
2'b10 : begin
o_strobe <= 1'b0;
step <= 2'b11;
end
2'b11 : begin
flag <= 1'b0;
// step <= 2'b00;
end
endcase
end
end
endmodule
Waveforms:
No strobe on 2nd data, step <= 2'b00 commented
http://i30.photobucket.com/albums/c315/soumyabumba/strobe_zpsc342b740.gif
Continuous toggling strobe, step <= 2'b00 uncommented
http://i30.photobucket.com/albums/c315/soumyabumba/pulse_strobe_zps8a1a5fb4.gif
Thank a lot Tim. I solved it and its only because of your helpful suggestion to add the flag and step waveforms. The main problem was that the case(switch) is getting executed on each clock cycle with the switch value of previous cycle and it is triggering the flag which is there under each statement. So I removed the case(i_switch) from always # (i_clock) and put it separately in an always # (i_switch) so that the case(switch) runs only when the switch is changed.
I am facing a minor problem though. Since I have added the always#(i_switch) block I am having doubts on initializing the i_switch input in the test bench file. If I initialize it before the global reset of 100# the o_data is starting as 00000000 instead of 00001111 i.e. the case statement started running even before the global reset completes. If i give i_switch as a stimulus after 100# a red line and a X is coming for i_switch for 100# indicating uninitialized input. I have attached the waveform and the solved code. Will there be any problem in implementation of this? Also I read somewhere all if statement must follow by else statement otherwise unwanted latching may occur, what can be written under else (flag == 0) condition under always #(i_clock)?
Waveform :
http://i30.photobucket.com/albums/c315/soumyabumba/strobe_solved_zps72b65a42.png
Solved Code:
`timescale 1ns / 1ps
module test3(
input i_clock,
input i_switch,
output reg [7:0] o_data = 8'b00001111,
output reg o_strobe = 1'b0
);
reg flag = 1'b0;
reg [1:0] step = 2'b00;
always # (i_switch)
begin
case (i_switch)
1'b0 : begin
o_data [7:0] <= 32'b00000000;
flag <= 1'b1;
end
1'b1 : begin
o_data [7:0] <= 32'b11111111;
flag <= 1'b1;
end
endcase
end
always # (posedge i_clock)
begin
if (flag == 1)
begin
case (step)
2'b00 : begin
o_strobe <= 1'b1;
step <= 2'b01;
end
2'b01 : begin
step <= 2'b10;
end
2'b10 : begin
o_strobe <= 1'b0;
step <= 2'b11;
end
2'b11 : begin
flag <= 1'b0;
step <= 2'b00;
end
endcase
end
end
endmodule
I have the following code.
CREATE OR REPLACE procedure BEFOR_VIP_RESET.CP_UPDATE_DTL_YHJ_SUM
is
cursor cur IS SELECT TRIM(DC.INV_NUM) INV_NUM,
SUM(DC.REDEEMVALUE) SUM_REDEEMVALUES
FROM DINV_COUPON DC
GROUP BY DC.INV_NUM;
INT_COUNT_DINV_COUPON_BY_INV number;
begin
for RUR1 in cur LOOP
BEGIN
SELECT COUNT(*) INTO INT_COUNT_DINV_COUPON_BY_INV
FROM DINV_DTL_YHJ DDY
WHERE TRIM(DDY.INV_NUM) = TRIM(RUR1.INV_NUM);
IF (INT_COUNT_DINV_COUPON_BY_INV != 0)
THEN
UPDATE DINV_DTL_YHJ D_D_Y
SET D_D_Y.REDEEMWAY = (RUR1.SUM_REDEEMVALUES/INT_COUNT_DINV_COUPON_BY_INV); --this error
END IF;
END;
END LOOP;
end CP_UPDATE_DTL_YHJ_SUM;
Error message:
ORA-06550: line 12, column 27:
PLS-00103: Encountered the symbol "END" when expecting one of the following:
. ( * # % & = - + ; < / > at in is mod remainder not rem
<an exponent (**)> <> or != or ~= >= <= <> and or like
When I debug I find INT_COUNT_DINV_COUPON_BY_INV and RUR1.INV_NUM have the right value.
When I change:
UPDATE DINV_DTL_YHJ D_D_Y
SET D_D_Y.REDEEMWAY = (RUR1.SUM_REDEEMVALUES/INT_COUNT_DINV_COUPON_BY_INV);
to
UPDATE DINV_DTL_YHJ D_D_Y
SET D_D_Y.REDEEMWAY = 66;
I also have the same error message.
It looks as if you forgot a WHERE clause on your UPDATE statement. Was this intentional?
Maybe something like:
WHERE TRIM(DDY.INV_NUM) = TRIM(RUR1.INV_NUM);