I have the following code.
CREATE OR REPLACE procedure BEFOR_VIP_RESET.CP_UPDATE_DTL_YHJ_SUM
is
cursor cur IS SELECT TRIM(DC.INV_NUM) INV_NUM,
SUM(DC.REDEEMVALUE) SUM_REDEEMVALUES
FROM DINV_COUPON DC
GROUP BY DC.INV_NUM;
INT_COUNT_DINV_COUPON_BY_INV number;
begin
for RUR1 in cur LOOP
BEGIN
SELECT COUNT(*) INTO INT_COUNT_DINV_COUPON_BY_INV
FROM DINV_DTL_YHJ DDY
WHERE TRIM(DDY.INV_NUM) = TRIM(RUR1.INV_NUM);
IF (INT_COUNT_DINV_COUPON_BY_INV != 0)
THEN
UPDATE DINV_DTL_YHJ D_D_Y
SET D_D_Y.REDEEMWAY = (RUR1.SUM_REDEEMVALUES/INT_COUNT_DINV_COUPON_BY_INV); --this error
END IF;
END;
END LOOP;
end CP_UPDATE_DTL_YHJ_SUM;
Error message:
ORA-06550: line 12, column 27:
PLS-00103: Encountered the symbol "END" when expecting one of the following:
. ( * # % & = - + ; < / > at in is mod remainder not rem
<an exponent (**)> <> or != or ~= >= <= <> and or like
When I debug I find INT_COUNT_DINV_COUPON_BY_INV and RUR1.INV_NUM have the right value.
When I change:
UPDATE DINV_DTL_YHJ D_D_Y
SET D_D_Y.REDEEMWAY = (RUR1.SUM_REDEEMVALUES/INT_COUNT_DINV_COUPON_BY_INV);
to
UPDATE DINV_DTL_YHJ D_D_Y
SET D_D_Y.REDEEMWAY = 66;
I also have the same error message.
It looks as if you forgot a WHERE clause on your UPDATE statement. Was this intentional?
Maybe something like:
WHERE TRIM(DDY.INV_NUM) = TRIM(RUR1.INV_NUM);
Related
I am trying to write a signal generator with VHDL and state machine approach. it needs to have two processes in an entity and I am doing everything just as same as the course I've passed but I am getting some errors around my process and I think something must be wrong with it. this is the code
entity pulse_generator is
port(clk : in std_logic;
output: out std_logic);
end pulse_generator;
architecture Behavioral of pulse_generator is
type state is (one, two, three, four);
signal nxt, pre: state;
begin
--upper
p1: process(clk)
begin
if (falling_edge(clk))then
pre <= nxt;
end if
end process p1;
--lower
p2: process(pre)
variable count: integer range 0 to 500;
begin
case pre is
when one =>
output <= '0';
count := count+1;
if (count = 300)then
nxt <= two;
count := 0;
else nxt <= one;
end if;
when two =>
output <= '1';
count := count+1;
if (count = 400)then
nxt <= three;
count := 0;
else nxt <= two;
end if;
when three =>
output <= '0';
count := count+1;
if (count = 500)then
nxt <= four;
count := 0;
else nxt <= three;
end if;
when four =>
output <= '1';
count := count+1;
if (count = 200)then
nxt <= one;
count := 0;
else nxt <= four;
end if;
end case;
end process p2;
end Behavioral;
and these are the errors
ERROR:HDLCompiler:806 - Line 19: Syntax error near "end".
ERROR:HDLCompiler:806 - Line 22: Syntax error near "process".
ERROR:HDLCompiler:806 - Line 23: Syntax error near "variable".
ERROR:HDLCompiler:806 - Line 59: Syntax error near "process".
ERROR:HDLCompiler:806 - Line 61: Syntax error near "Behavioral"
what am I doing wrong?
I have tried to execute the following script:
SET TERM !! ;
EXECUTE BLOCK AS
DECLARE I INTEGER;
BEGIN
I = 296;
WHILE (I < 500) DO
BEGIN
UPDATE DD_TABLE SET DATA_FLOW = DATA_RAW
WHERE DATA_COUNTER = I
I = I + 1;
END
END!!
SET TERM;!!
and I got the error:
Engine Code : 335544569
Engine Message :
Dynamic SQL Error
SQL error code = -104
Token unknown - line 15, column 4
I'm not sure exactly what I missed.
I'm kinda new to mysql and i'm trying to do a relatively simple trigger for an app i'm working on, but i'm afraid I can't seem to find where the error is, as my teacher isn't really helpful... Hope you guys can help me... Here's the code:
CREATE OR REPLACE
TRIGGER TR_NUEVOMECA AFTER INSERT ON MECADISTRIBUIDOS FOR EACH ROW
DECLARE
VARIABLEBUCLE NUMBER;
MESACTUAL NUMBER;
BEGIN
SET MESACTUAL=(SELECT EXTRACT(MONTH FROM NOW()));
IF (NEW.TIPOASC == 1) THEN
SET VARIABLEBUCLE = 12;
ELSIF (NEW.TIPOASC == 2) THEN
SET VARIABLEBUCLE = 6;
ELSIF(NEW.TIPOASC == 3) THEN
SET VARIABLEBUCLE = 4;
ELSIF(NEW.TIPOASC == 4) THEN
SET VARIABLEBUCLE = 3;
ELSIF(NEW.TIPOASC == 6) THEN
SET VARIABLEBUCLE = 2;
ELSIF(:NEW.TIPOASC == 12) THEN
SET VARIABLEBUCLE = 1;
END IF;
WHILE(VARIABLEBUCLE>0) DO
INSERT INTO MANTENIMIENTOS VALUES(0,:NEW.IDENTIF,NULL,NULL,NULL,MESACTUAL);
SET VARIABLEBUCLE=VARIABLEBUCLE - 1;
SET MESACTUAL=MESACTUAL + NEW.TIPOASC;
IF(MESACTUAL>12) THEN
SET MESACTUAL=MESACTUAL%12;
END IF;
END WHILE;
END;
Here's the log photo:
enter image description here
Thanks in advance guys.
I keep getting errors below in ISE, and can not figure out the real problems. anyone has any clues?
error messages:
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 29: Syntax error near "posedge".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 39: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 43: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 47: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 50: Syntax error near "end".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 54: Syntax error near "posedge".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 64: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 68: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 72: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 75: Syntax error near "end".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 88: Syntax error near "posedge".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 98: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 102: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 106: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 109: Syntax error near "end".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 113: Syntax error near "posedge".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 123: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 127: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 131: Syntax error near "<=".
and here is my code:
`timescale 1ns/1ps
module QFC_A #
(
parameter SPI_CYCLE = 100000,
parameter MASTER_ID = 8'h66,
parameter SLAVE_ID = 8'h66
)
(
input i_axi_lite_s_aclk,
input i_rst,
input i_din,
output o_en,
output o_dout
);
reg [255:0] r_frame_message;
reg [3:0] r_cnt_message;
wire [31:0] w_frame_word_message;
wire w_message_rd_en;
wire w_id_match_message;
wire w_message_empty;
wire w_message_ready;
always # (posedge i_axi_lite_s_aclk & posedge i_rst)
begin
if (i_rst)
begin
r_frame_message <= 256'h0;
end
else
begin
if (w_id_match_message & (r_cnt_message != 4'hf))
begin
r_frame_message <= {224'h0, w_frame_word_message};
end
else if (w_message_rd_en & w_message_empty)
begin
r_frame_message <= 256'h0;
end
else if (w_message_rd_en)
begin
r_frame_message <= {r_frame_message[223:0], w_frame_word_message};
end
end
end
assign w_id_match_message = (w_frame_word_message[23:16] == MASTER_ID)? 1'b1 : 1'b0;
always # (posedge i_axi_lite_s_aclk & posedge i_rst)
begin
if (i_rst)
begin
r_cnt_message <= 4'h0;
end
else if (w_message_rd_en)
begin
if (w_id_match_message)
begin
r_cnt_message <= 4'h0;
end
else if (r_cnt_message == 4'hf)
begin
r_cnt_message <= 4'h0;
end
else
begin
r_cnt_message <= r_cnt_message + 4'h1;
end
end
end
assign w_message_ready = (r_cnt_message == 4'hf & ~w_send_ready)? 1'b1 : 1'b0;
reg [255:0] r_frame_data;
reg [3:0] r_cnt_data;
wire [31:0] w_frame_word_data;
wire w_data_rd_en;
wire w_id_match_data;
wire w_data_empty;
wire w_data_ready;
always # (posedge i_axi_lite_s_aclk & posedge i_rst)
begin
if (i_rst)
begin
r_frame_data <= 256'h0;
end
else
begin
if (w_id_match_data & (r_cnt_data != 4'hf))
begin
r_frame_data <= {224'h0, w_frame_word_data};
end
else if (w_data_rd_en & w_data_empty)
begin
r_frame_data <= 256'h0;
end
else if (w_data_rd_en)
begin
r_frame_data <= {r_frame_data[223:0], w_frame_word_data};
end
end
end
assign w_id_match_data = (w_frame_word_data[23:16] == MASTER_ID)? 1'b1 : 1'b0;
always # (posedge i_axi_lite_s_aclk & posedge i_rst)
begin
if (i_rst)
begin
r_cnt_data <= 4'h0;
end
else if (w_data_rd_en)
begin
if (w_id_match_data)
begin
r_cnt_data <= 4'h0;
end
else if (r_cnt_data == 4'hf)
begin
r_cnt_data <= 4'h0;
end
else
begin
r_cnt_data <= r_cnt_data + 4'h1;
end
end
end
assign w_data_ready = (r_cnt_data == 4'hf & ~w_send_ready)? 1'b1 : 1'b0;
reg [255:0] r_frame_rec;
reg [3:0] r_cnt_rec;
wire[31:0] w_frame_word_rec;
wire w_rec_en;
wire w_id_match_rec;
wire w_rec_ready;
wire w_rec_success;
always # (posedge i_axi_lite_s_aclk & posedge i_rst)
begin
if (i_rst)
begin
r_frame_rec <= 256'h0;
end
else
begin
if (w_id_match_rec & (r_cnt_rec != 4'hf))
begin
r_frame_rec <= {224'h0, w_frame_word_rec};
end
else if (w_rec_en)
begin
r_frame_rec <= {r_frame_rec[223:0], w_frame_word_rec};
end
end
end
assign w_id_match_rec = (w_frame_word_rec[23:16] == SLAVE_ID)? 1'b1 : 1'b0;
always # (posedge i_axi_lite_s_aclk & posedge i_rst)
begin
if (i_rst)
begin
r_cnt_rec <= 4'h0;
end
else if (w_rec_en)
begin
if (w_id_match_rec)
begin
r_cnt_rec <= 4'h0;
end
else if (r_cnt_rec == 4'hf)
begin
r_cnt_rec <= 4'h0;
end
else
begin
r_cnt_rec <= r_cnt_rec + 4'h1;
end
end
end
assign w_rec_ready = (r_cnt_rec == 4'hf)? 1'b1 : 1'b0;
assign w_rec_success = ((w_rec_ready) & (r_frame_rec[251] == 1'b1) & (checksum(r_frame_rec[239:16]) == r_frame_rec[15:0]))? 1'b1 : 1'b0;
reg [2:0] r_current_state;
reg [2:0] r_next_state;
reg [16:0] r_cycle_timer;
reg [14:0] r_trans_timer;
reg [1:0] r_cycle_s;
reg [223:0] r_payload;
reg [255:0] r_frame_send;
wire w_cycle;
wire w_cycle_pos;
wire w_state_start;
localparam IDLE = 3'h0;
localparam SEND_MSG = 3'h1;
localparam RESEND_MSG = 3'h2;
localparam SEND_DATA = 3'h3;
localparam RCG_ACK = 3'h4;
localparam CHANGE_TLG = 3'h5;
localparam ABORT_MSG = 3'h6;
always # (posedge i_axi_lite_s_aclk & posedge i_rst)
begin
if (i_rst)
begin
r_cycle_timer <= 16'h0;
end
else if (r_cycle_timer < SPI_CYCLE)
begin
r_cycle_timer <= r_cycle_timer + 16'h1;
end
else
begin
r_cycle_timer <= 16'h0;
end
end
assign w_cycle = (r_cycle_timer == SPI_CYCLE)? 1'b1 : 1'b0;
always # (posedge i_axi_lite_s_aclk & posedge i_rst)
begin
if(i_rst)
begin
r_cycle_s <= 2'h0;
end
else
begin
r_cycle_s <= {r_cycle_s[0], w_cycle};
end
end
assign w_cycle_pos = (~r_cycle_s[1] & r_cycle_s[0]);
function reg [15:0] checksum (input reg [223:0] r_frame)
begin
integer i;
reg [15:0] r_sum_1;
reg [15:0] r_sum_2;
r_sum_1 = 16'hff;
r_sum_2 = 16'hff;
for (i = 0; i < 28; i++)
begin
r_sum_1 = r_sum_1 + r_frame[(223-8*i)-:8];
r_sum_2 = r_sum_1 + r_sum_2;
if (i == 20)
begin
r_sum_1 = ( r_sum_1 >> 8 ) + ( r_sum_1 & 8'hff);
r_sum_2 = ( r_sum_2 >> 8 ) + ( r_sum_2 & 8'hff);
end
end
r_sum_1 = ( r_sum_1 >> 8 ) + ( r_sum_1 & 8'hff);
r_sum_2 = ( r_sum_2 >> 8 ) + ( r_sum_2 & 8'hff);
r_sum_1 = ( r_sum_1 >> 8 ) + ( r_sum_1 & 8'hff);
r_sum_2 = ( r_sum_2 >> 8 ) + ( r_sum_2 & 8'hff);
checksum = (r_sum_1 << 8) | r_sum_2;
end
endfunction
always # (*)
begin
case (r_current_state)
IDLE: begin
r_next_state = SEND_DATA;
r_frame_send = {8'h90, MASTER_ID, 240'h0};
end
SEND_MSG: begin
r_next_state = RCG_ACK;
if (w_state_start)
begin
w_message_rd_en = 1'b1;
w_send_ready = 1'b0;
w_state_start = 1'b0;
end
if (r_frame_message == 256'h0)
begin
w_message_rd_en = 1'b0;
r_frame_send = {r_frame_send[], MASTER_ID, 240'h0};
end
else if
end
RCG_ACK: begin
if (w_rec_success)
begin
r_next_state = CHANGE_TLG;
end
else if (r_resend_cnt == 2'b11)
begin
r_next_state = ABORT_MSG;
end
end
endcase
end
endmodule
The likely cause of this error is from the & in # (posedge i_axi_lite_s_aclk & posedge i_rst). It is illegal syntax and I am guessing it is confusing the parser, making the error appear by the non-blocking assignment (<=). Change these & to or (I believe IEEE 1364-2001 also supports , as a sensitivity list separator but I do not have my LRM on hand to validate).
Eg: # (posedge i_axi_lite_s_aclk or posedge i_rst)
There are plenty of other syntax errors. Missing semicolon in the function header, dangling else if, undeclared identifiers, etc. I'm not going to fix them for you.
FYI:
& is a bitwise and operator, which is different then the logical and operator &&. You are using & in places where && would be recommended. I suggest you study the differences between logical and bitwise operators.
For many synthesizers using ? : creates an explicit 2-to-1 mux. In all the cases you use ? : the select value is the same as the output value. So you may just be wasting space.
I would suggest changing assign w_message_ready = (r_cnt_message == 4'hf & ~w_send_ready)? 1'b1 : 1'b0; to assign w_message_ready = (r_cnt_message == 4'hf && !w_send_ready);. Functionally they are identical, but the latter is more explicit and concise.
So i have a tool that call procedure.
Tool looks like that:
call Attach_test('select TTID from alerts.status where Class in (73000,8891) and to_int(TTID) > 0 and ServerSerial in ($selected_rows.Serial)',[ $selected_rows.Serial ]); flush iduc;
it should get TTID (that field have only one of many selected alarms ) and array of server serials of selected alarms.
Then all this data is transfered to SQL procedure that looks like:
declare
tempservser integer; k integer;
begin
for k = 1 to array_len(serserial) do
begin
set tempservser = serserial[k];
update alerts.status set ParentTT = parentttid, TTFlag = 2 where ServerSerial = tempservser and TTID = '' ;
end;
end
Parameters:
in parentttid Char(11)
in serserial array of Integer
And here comes the trouble - procedure do nothing. There is no errors or something but there is no update on selected alarms.
I want it to work like this - you select many alarms with only one that have TTID, run this tool that set ParentTT = TTID on every other of selected alarms.
OS ver. 8.1
Sorry for my english
I figured out how to do it:
Tool
call AttachSelectedToTTID([ $selected_rows.Serial ],[ $selected_rows.ParentTT ]);
flush iduc;
Procedure
declare
tempservser integer; k integer;n integer;partt char(15);
begin
for n = 1 to array_len(ttid) do
begin
if (ttid[n] != '' ) then
set partt = ttid[n];
end if;
end;
for k = 1 to array_len(serserial) do
begin
set tempservser = serserial[k];
update alerts.status set ParentTT = partt,TTFlag = 2 where Serial = tempservser and TTID = '';
end;
end
Parameters:
in ttid array of Char(15)
in serserial array of Integer