I have a little question related to my VHDL code. I have to create a simulation for 1 bit of ALU. I created a D flip-flop and a Full Adder, and now I have to connect them with some simple logical gates. How can I do to use variables from this 2 entities to do this?
My code is:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY D_flipflop IS PORT (
D, Clock: IN STD_LOGIC;
Q: OUT STD_LOGIC);
END D_flipflop;
ARCHITECTURE Behavior OF D_flipflop IS
BEGIN
PROCESS(Clock)
BEGIN
IF Clock'EVENT AND Clock = '0' THEN
Q<= D;
END IF;
END PROCESS;
END Behavior;
ENTITY fa IS PORT (
Ci, Xi, Yi: IN STD_LOGIC ;
Ci1, Si: OUT STD_LOGIC) ;
END fa;
ARCHITECTURE Dataflow OF fa IS
BEGIN
Ci1 <= (Xi AND Yi) OR (Ci AND (Xi XOR Yi));
Si <= Xi XOR Yi XOR Ci;
End Dataflow ;
Related
I'm having "Iteration limit reached" error in a simple FSM.
This is a part of of a bigger FSM I have to do for a class assignment, and I tracked the problem to this specific part.
The FSM will be controlling a counter, the state IDLE waits for inputs, ZERO sets the counter to zero, and the INCREMENT state increments the counter by one.
When simulating, the error occurs at the first time the input "inc" is high and the clock rises.
If I change the statement "temp := temp + 1;" for "temp := anything" the error stops. I really don't know what can be wrong, as for what I have found this error occurs when changing signals in the process sensitivity list inside the process itself.
I'm using Quartus II for the simulation.
Sorry for english mistakes.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
entity fsm is
port
(
clock: in std_logic;
reset: in std_logic;
inc: in std_logic;
count: out std_logic_vector (13 downto 0);
cur_state: out std_logic_vector (1 downto 0)
);
end fsm;
architecture behaviour of fsm is
type state_type is (IDLE, INCREMENT, ZERO);
signal PS, NS: state_type;
begin
sync_proc: process (clock, reset)
begin
if (reset = '1') then
PS <= ZERO;
elsif (rising_edge(clock)) then
PS <= NS;
end if;
end process sync_proc;
comb_proc: process (PS, inc)
variable temp: unsigned (13 downto 0);
begin
case PS is
when IDLE =>
if (inc = '1') then
NS <= INCREMENT;
else
NS <= IDLE;
end if;
when INCREMENT =>
temp := temp + 1;
NS <= IDLE;
when ZERO =>
temp := "00000000000000";
NS <= IDLE;
when others =>
NS <= IDLE;
end case;
count <= std_logic_vector(temp);
end process comb_proc;
with PS select
cur_state <= "00" when IDLE,
"01" when INCREMENT,
"10" when ZERO,
"11" when others;
end behaviour;
You have a very serious CONCEPTUAL mistake in your case statement. Because it produces a combinational circuit (the combinational part of your FSM), it does not have memory, so it can't implement the equation "temp := temp + 1" (because, having no memory, it doesn't know what the value of temp is).
You can see more about this in chapter 11 of "Finite State Machines in Hardware...", by V.Pedroni, published by MIT.
So I am designing a serial squarer. My program takes a basic binary counter, and uses each count of the counter to calculate squares in series. When I try to synthesize my code, depending on how I arrange my code, either synthesis runs almost infinitely, or the synthesis run just crashes entirely. So I figured that I cannot update my signal r_final => r_final + r_min1 because I remember that not being a thing in vhdl. So I have decided that I need to set r_final to a variable instead of a signal. I'm not sure how I should declare r_final as a variable. Can anyone provide some insight on how I can get r_final to update with itself?
This is my main code, the part in question is under the comment -- next state logic:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity serial_square is
port(
clk, reset: in std_logic;
q: out std_logic_vector (3 downto 0));
end serial_square;
architecture behavioral of serial_square is
signal r_reg : unsigned (3 downto 0) := "0000";
signal r_next : unsigned (3 downto 0);
signal r_2i : unsigned (3 downto 0);
signal r_min1 : unsigned (3 downto 0);
shared variable r_final : unsigned := "0000";
begin
-- register
process(clk,reset)
begin
if (reset='1') then
r_reg <= (others => '1');
elsif (clk'event and clk='1') then
r_reg <= r_final;
end if;
end process;
-- next state logic
r_next <= r_reg +1; -- r_reg + 1
r_2i <= r_next(2 downto 0) & '0'; -- multiply by 2
r_min1 <= r_2i - 1; -- minus one
r_final := r_min1 + r_final; -- add r_min1 to r_final, output should be the count r_next, squared.
--output logic
q <= std_logic_vector(r_reg);
end behavioral;
The update of r_final must be in the clocked process, so the next value is generated through a synchronous (clocked) update, since this is the structure that matches the available hardware.
Shared variables can't be synthesized, but is a feature only used for test benches.
I just started with VHDL so this is hopefully a pretty basic question, My problem is that i want to code this ciruit! --> http://postimg.org/image/rrd2czsox/ <--
In my ciruit as u can see, p and q both acts as input & outputs signal.
Here is my code for this ciruit!
library ieee;
use ieee.std_logic_1164.all;
entity pracc is
port(a,b,s,p,q : in std_logic;
y,z: out std_logic);
end pracc;
architecture Exercise5 of pracc is
begin
p <= a AND b;
q <= NOT p;
y <= p;
z <= q;
end architecture;
But i can't compile this. Even if i change p & q as output signals!
Glad for help!
p and q are not inputs to your overall circuit - they're intermediate/local signals. Declare them like so:
architecture ...
signal p,q : std_logic;
begin
...
Local signals connect logic within a component. Ports connect your component to other things.
Declare p,q as buffer instead of input or output.
Buffers are outputs that are again used to compute other outputs.
Quite new to VHDL here, so I'm not entirely sure if this is feasible at all, but here goes:
In my test code for some RAM, I have 2 8-bit std_logic_vector variables wdata_a_v and wdata_b_v. This is all I need for the current setup, but if the ratio of read to write data length changes, I will need more variables of the name wdata_*_v. I'm trying to write the code generically so that it will function for any amount of these variables, but I don't want to declare 26 of them in the code when I will likely only need a few.
It would be nice if there was a way to declare a variable like so:
variable wdata_*_v : std_logic_vector (7 downto 0);
that would, behind the scenes, declare all of the variables that fit this framework so that I could write a loop without worrying about running out of variables.
If there's a way to write a function or procedure etc. to make this work, that would be excellent.
Yes, you can go with a 2d array, recipe:
entity TestHelper is
generic (n: natural range 2 to 255 := 8);
end TestHelper;
architecture behavioral of TestHelper is
type array2d is array (n-1 downto 0) of std_logic_vector(7 downto 0);
begin
process
variable a : array2d;
begin
a(0)(0) := '0';
end process;
end architecture behavioral;
EDIT: Now to use it and create similar code for each of wdata_*_v:
process
variable wdata_v : array2d;
begin
someLabel: for i in 0 to n-1 generate
wdata_v(i)(0) := '0';
x <= y and z;
...
end generate;
x <= '1';
...
anotherLabel: for i in 1 to n generate
...
end generate;
...
end process;
I'm still trying to get used to some of the quirks of VHDL and I'm having a bit of an issue. First off, I understand that shift operators like rol, ror, ssl, srl, etc. are not synthesizeable. The purpose of this lab is to use a golden model to check against a synthesizeable version of the same thing in a testbench.
Now, the purpose of this program is to convert thermometer code into a 3-bit binary number. So, in other words, thermometer code "00000001" = "001", "00000011" = "010", "00000111" = "011", etc. I'm basically trying to count the number of 1's in the string from right to left. There will be no case where a '0' is placed between the string of 1's, so the vector "00011101" is invalid and will never occur.
I've devised a non-synthesizeable (and so far, non-compile-able) algorithm that I can't figure out how to get working. Basically, the idea is to read the thermometer code, shift it right and increment a counter until the thermometer code equals zero, and then assign the counter value to the 3-bit std_logic_vector. Below is the code I've done so-far.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity therm2bin_g is
port(therm : inout std_logic_vector(6 downto 0); -- thermometer code
bin : out std_logic_vector(2 downto 0); -- binary code
i : integer range 0 to 7);
end therm2bin_g;
architecture behavioral_g of therm2bin_g is
begin
golden : process(therm)
begin
while(therm /= "00000000") loop
therm <= therm srl 1;
i = i + 1;
end loop;
bin <= std_logic'(to_unsigned(i,3));
end process golden;
behavioral_g;
here's a version that is synthesisable. the while loop is replaced by a for loop. srl is implemented explicitly:
entity therm2bin_g is
port(therm : inout std_logic_vector(6 downto 0); -- thermometer code
bin : out std_logic_vector(2 downto 0); -- binary code
i : out integer range 0 to 7);
end therm2bin_g;
architecture behavioral_g of therm2bin_g is
begin
golden : process(therm)
variable i_internal: integer range 0 to 7;
begin
i_internal:=0;
for idx in 0 to therm'length loop
if therm/="0000000" then
therm<='0' & therm(therm'left downto 1);
i_internal := i_internal + 1;
end if;
end loop;
bin<=std_logic_vector(to_unsigned(i_internal,bin'length));
i<=i_internal;
end process golden;
end behavioral_g;
"... operators like rol, ror, ssl, srl, etc. are not synthesizeable..."
Who says that on who's authority? Have you checked? On which synthesis tool? Was it a recent version, or a version from the early 1990s?
Note that the argument that some tools might not support it is just silly. The fact that some kitchens might not have an oven does not stop people from writing recipes for cake.