I am using Xilinx Vivado 2015.2 64 bit.
While running the following simulation I am getting the following error:
FATAL_ERROR: Vivado simulator Kernel has discovered an exceptional condition from which it cannot recover. Process will terminate.
Now the module:
module q();
wire a,b;
endmodule
Test bench for the module:
module tb_q();
reg a,b;
int gan [4] [$];
initial
begin
gan[2].push_back(67);
$monitor("gan= %p",gan);
end
endmodule
Any help will be deeply appreciated.
Thanks.
I believe simulator support of SystemVerilog is limited to a synthesizable subset. http://www.xilinx.com/support/answers/59002.html
Related
I'm attempting to use Yosys to generate an edif file that I then use with Vivado tcl scripting to generate a bitstream for an Artix 7 (xc7a15t) FPGA. However, Vivado seems to have trouble with a few of the cells in the edif file.
When I use the same verilog and constraints file completely in Vivado the bitstream is created fine, and it works as expected when I load it onto the FPGA.
I've modeled my workflow off the example here.
Specifically, I'm using the following shell script as a frontend for the yosys and Vivado commands:
#!/bin/bash
yosys run_yosys.ys
vivado -nolog -nojournal -mode batch -source run_vivado.tcl
run_yosys.ys:
read_verilog top.v
synth_xilinx -edif top.edif -top top
run_vivado.tcl
read_xdc top.xdc
read_edif top.edif
link_design -part xc7a15tftg256-1 -top top
opt_design
place_design
route_design
report_utilization
report_timing
write_bitstream -force top.bit
top.v (simple blinky example):
`default_nettype none
module top (
input wire clk,
output reg led);
reg [24:0] cnt = 25'b0;
always #(posedge clk) begin
cnt <= cnt + 1'b1;
if (cnt == 25'b0) begin
led <= !led;
end
else begin
led <= led;
end
end
endmodule // top
top.xdc:
create_clock -period 25.000 -name clk -waveform {0.000 12.500} [get_ports clk]
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN N11} [get_ports clk]
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN D1} [get_ports led]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
The Vivado tcl command opt_design generates the following error:
ERROR: [DRC INBB-3] Black Box Instances: Cell 'GND' of type 'GND/GND' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
I get the same error for cell 'VCC'.
I also get a warning related to this when calling link_design:
CRITICAL WARNING: [Netlist 29-181] Cell 'GND' defined in file 'top.edif' has pin 'Y' which is not valid on primitive 'GND'. Instance 'GND' will be treated as a black box, not an architecture primitive
Am I using Yosys incorrectly here? What's the correct flow for this? I'm new to Yosys, so forgive me if I've missed something obvious.
I'm using Yosys 0.8+147 and Vivado 2017.2
The solution is in the Yosys user manual. Vivado is complaining about the 'VCC' and 'GND' cells, so we must pass the -nogndvcc option to write_edif. As explained in the description for the -nogndvcc option, to do this we must use hilomap to associate VCC and GND with custom drivers. The full xilinx synthesis is achieved with:
synth_xilinx -top top
hilomap -hicell VCC P -locell GND G
write_edif -nogndvcc top.edif
I've been testing yosys for some use cases.
Version: Yosys 0.7+200 (git sha1 155a80d, gcc-6.3 6.3.0 -fPIC -Os)
I wrote a simple block which converts gray code to binary:
module gray2bin (gray, bin);
parameter WDT = 3;
input [WDT-1:0] gray;
output [WDT-1:0] bin;
assign bin = {gray[WDT-1], bin[WDT-1:1]^gray[WDT-2:0]};
endmodule
This is an acceptable and valid code in verilog, and there is no loop in it.
It passes compilation and synthesis without any warnings in other tools.
But, when I run in yosys the next commands:
read_verilog gray2bin.v
scc
I get that a logic loop was found:
Found an SCC: $xor$gray2bin.v:11$1
Found 1 SCCs in module gray2bin.
Found 1 SCCs.
The next code, which is equivalent, pass the check:
module gray2bin2 (
gray,
bin
);
parameter WDT = 3;
input [WDT-1:0] gray;
output [WDT-1:0] bin;
assign bin[WDT-1] = gray[WDT-1];
genvar i;
generate
for (i = WDT-2; i>=0; i=i-1) begin : gen_serial_xor
assign bin[i] = bin[i+1]^gray[i];
end
endgenerate
endmodule
Am I missing a flag or synthesis option of some kind?
Using word-wide operators this circuit clearly has a loop (generated with yosys -p 'prep; show' gray2bin.v):
You have to synthesize the circuit to a gate-level representation to get a loop-free version (generated with yosys -p 'synth; splitnets -ports; show' gray2bin.v, the call to splitnets is just there for better visualization):
The answer given by CliffordVienna indeed gives a solution, but I also want to clarify that that it's not suitable to all purposes.
My analysis was done for the purpose of formal verification. Since I replaced the prep to synth to solve the falsely identified logic loops, my formal code got optimized. Wires which I've created that were driven only by the assume property pragma, were removed - this made many assertions redundant.
It's not correct to reduce any logic for the purpose of behavioral verification.
Therefore, if the purpose is to prepare a verification database, I suggest not to use the synth command, but to use a subset of commands the synth command executes.
You can find those commands under:
http://www.clifford.at/yosys/cmd_synth.html
In general, I've used all the commands specified in the above link that do not optimize logic:
hierarchy -check
proc
check
wreduce
alumacc
fsm
memory -nomap
memory_map
techmap
abc -fast
hierarchy -check
stat
check
And everything works as expected.
I have a couple of errors in my verilog code that pop up when I compile. I believe they are all related. But I can't figure out what the error is. Any help will be greatly appreciated.
The errors are: Two for the input
vlog_a: Error 31004 Syntax error near `input' found
blog_a: Error 31004 Syntax error near 'output' found
module threeBitComparator;
input A2,A1,A0;
input B2,B1,B0;
output E,GE; //E-Equal, GE-Greater than or Equal to
wire X1,X2,X3; //xnor gate
wire Y1,Y2,Y3,Y4,Y5,Y6; // and & or gates
xnor
G1a(X1,A2,B2),
G1b(X2,A1,B1),
G1c(X3,A0,B0);
and
G2a(Y1,A2,~B2),
G2b(Y2,A1,~B1),
G2c(Y3,A0,~B0),
G2d(Y4,X1,Y2),
G2e(Y5,X1,X2,Y3),
G2f(E,X1,X2,X3);
or
G3a(Y6,Y1,Y4,Y5),
G3b(GE,Y6,E);
endmodule
You declared your inputs and outputs but you haven't declared a port list. Your module header needs to look like below code to be IEEE 1364-1995 complaint
module threeBitComparator(A2,A1,A0,B2,B1,B0,E,GE); // <-- port list
input A2,A1,A0;
input B2,B1,B0;
output E,GE; //E-Equal, GE-Greater than or Equal to
Or you can use the ANSI style header introduce in IEEE Std 1364-2001. This style works on any modern Verilog simulator.
module threeBitComparator(
input A2,A1,A0,
input B2,B1,B0,
output E,GE ); //E-Equal, GE-Greater than or Equal to
I think you forgot to declare your input and output in the module port lists. Adding A2, A1..., etc to the port list will solve the compilation errors.
You can check the updated code here.
My top level verilog module declares signals for the four LEDs on the myStorm ice40 board, which are labelled "LED1-LED4".
module top (
output [4:1] LED
);
assign LED = 4'b1010;
endmodule
I use the same numbering in the .pcf file:
set_io LED[1] 37
set_io LED[2] 38
set_io LED[3] 39
set_io LED[4] 41
But in the .blif output, yosys has renumbered the signals:
.model top
.inputs
.outputs LED[0] LED[1] LED[2] LED[3]
...
so arachne-pnr complains:
top.pcf:4: fatal error: no port `LED[4]' in top-level module `top'
Does yosys expect that top level vector ports are always numbered from zero?
The reason for this is that the Yosys BLIF back-end was not using the hints for start offset and direction (upto/downto) stored in a Yosys Wire object for generating the single-bit net names.
This is now fixed in commit 5c2c78e2dd. Thanks for bringing this to my attention.
Update to latest git head of Yosys and you should get the results that you are expecting.
I am writing a simple flipflop module in verilog and I am trying to write a top level module in instantiate my flipflop module and simulate it in ModelSim.
Here is my code below,
module flipflop(clck,D,Q);
input clck,D;
output Q;
wire R,S,S_g,R_g,Qa,Qb;
assign R = ~D;
assign S = D;
nand(S_g,S,clck);
nand(R_g,R,clck);
nand(Qa,S_g,Qb);
nand(Qb,R_g,Qa);
assign Q = Qa;
endmodule
module TopLevel();
reg clck;
reg Q;
wire D;
flipflop p1(clck,D,Q);
always begin
#5 clck <=1;
#5 clck <=0;
end
endmodule
When I compile this code it runs fine, but when I try to simulate it, I get the following error:
# ** Error: (vsim-3053) C:/altera/13.1/FlipFlopsProjects/flipflop.v(30): Illegal output or inout port connection for "port 'Q'".
Any ideas or thoughts?
Error was in the declaration of inputs for the top level module...they needed to be wires, not regs
In top module, Q needed to be regs and D needed to be wires.