hardware

hardware

What is the minimum size of an address register for a computer with 5TB of memory?

mem_test.bat file does not execute

EDID signal with DVI Splitter

Discussion: CMSIS VS Hardware Abstraction Layer by method of Texas Instruments

Technology/Hardware that can detect contents of warehouse goods

Multiseat setup for fun and profit: hypervisors and other choices

PROTEUS: How to add a binary firmware, from an unsupported compiler?

Hardware implementation of Data Encryption Standard (S-boxes /permutations)

Reducing the impact on diskspace when loading new software on a dev machine.

What is the common way to discovery physical servers in a datacentre?

Design a XOR gate and a XNOR gate using a 2 to 4 Demultiplexer and 2-input OR gates

Max length of signal in gpio

Is it possible to implement alle logical functions only with XNOR and AND-gates??(Hardware)

Maximum Throughput of a grid of hardware logic operations

How is PCI ROM shadowed?

Sensors that detects and simulate human emotions

How can I generate a hexfile from C code for testing a 32-bit RISC-V hardware design?

Openstack - hardware requirements

What IoT project to develop modules connected by BLE was funded on Kickstarter?

CRT displays for DEC PDP-8 series

Grove Seeed Studio sensors not working properly with Intel Edison

Reverse engineering a network interface [closed]

How are bytes mapped to AXI4 bus on a little endian system

OpenSolaris 11.2 - understanding some of prtconf output

Distributed Z3 and best hardware for each node

Flash Player Hardware decoding use or not?

How does Google, Facebook etc. deal with memory corruption etc

No data on the "D1" and "D2" register of the MS5637 Altimeter/pressure sensor

how many bits represent the value 2G

Incrementing address counter, ST7735 display driver

Using a transcription pedal as an audio control surface

VPI vpi_put_value on nets

How many nand gates does a computer actually need to operate?

Passing a module name as parameter

Does laptop Embedded Controller have limited writes?

CatapultC reverse bit order

How 16 bit array needs 5 bit address (Xilinx Vivado HLS)?

How to create a n-bit counter using GAL, programming in WinCUPL

Designing a Computer for Spatially-Explicit Modeling in NetLogo

How to support architecture reuse with minor differences

Shift Register Vs Multiplexer [closed]

Value U is missing in select

Why the INOUT doesn't work?

Can cc2541 be the role of observer and peripheral at the same time?

how single irq line is shared at physical hardware among multiple devices

How does an O.S. or a high level abstraction layer gain knowledge of the hardware using the device driver?

Cause of gated clock

von neumann vs harvard architecture

Hacking computer hardware to do experiment control

VHDL Dynamic slicing using mathematical expression

For loop is not unrolling in chisel

Hardware address of network interface using ioctl on AIX

Variable assignment in SystemVerilog generate statement

How to detect active video card and retrieve hardware ids?

Baud Rate Clock VHDL -- floating point exception error and/or style issues

Why is it not possible to read an unaligned word in one step?

How to determine whether a hardware or a software watchdog is implemented on the machine?

Verilog implementation of serial receiver not behaving like simulation (in fact, it's doing nothing)

Wifi signal logger device

Any wireless chipsets with open specifications?

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